US 12,243,818 B2
Memory device and method of manufacturing the same
Jin Ha Kim, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Dec. 16, 2021, as Appl. No. 17/552,944.
Claims priority of application No. 10-2021-0100874 (KR), filed on Jul. 30, 2021.
Prior Publication US 2023/0035588 A1, Feb. 2, 2023
Int. Cl. H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 23/535 (2006.01); H10B 41/27 (2023.01); H10B 43/27 (2023.01)
CPC H01L 23/5283 (2013.01) [H01L 23/53266 (2013.01); H01L 23/535 (2013.01); H10B 41/27 (2023.02); H10B 43/27 (2023.02)] 25 Claims
OG exemplary drawing
 
1. A memory device comprising:
interlayer insulation layers spaced apart from each other and stacked;
gate lines formed between the interlayer insulation layers; and
a plug vertically passing through the interlayer insulation layers and the gate lines,
wherein each of the gate lines comprises:
a barrier layer formed along an inner wall of each of the interlayer insulation layers and the plug;
a first conductive layer surrounded by the barrier layer; and
a second conductive layer surrounded by the first conductive layer, wherein a material of the second conductive layer is different from a material of the first conductive layer, and wherein a size of the second conductive layer is variable along a direction in which the gate lines extend,
wherein the material of the second conductive layer has a melting point lower than the material of the first conductive layer.