US 12,243,815 B2
Semiconductor device and method of fabricating the same
Eui Bok Lee, Seoul (KR); Wandon Kim, Seongnam-si (KR); and Rakhwan Kim, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Feb. 25, 2022, as Appl. No. 17/680,507.
Claims priority of application No. 10-2021-0097640 (KR), filed on Jul. 26, 2021.
Prior Publication US 2023/0022545 A1, Jan. 26, 2023
Int. Cl. H01L 23/522 (2006.01); H01L 21/768 (2006.01); H10D 64/23 (2025.01)
CPC H01L 23/5226 (2013.01) [H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H10D 64/256 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a front-end-of-line (FEOL) layer, which includes a plurality of individual devices, on a substrate; and
a first metal layer, a second metal layer, and a third metal layer sequentially stacked on the FEOL layer,
wherein the second metal layer comprises an interlayer insulating layer and an interconnection line in the interlayer insulating layer,
wherein the interconnection line comprises:
a lower via portion electrically connected to the first metal layer;
an upper via portion electrically connected to the third metal layer; and
a line portion between the lower via portion and the upper via portion,
wherein the interlayer insulating layer comprises a lower interlayer insulating layer and an upper interlayer insulating layer on the lower interlayer insulating layer,
wherein a lower part of the interconnection line is buried in the lower interlayer insulating layer,
wherein an upper part of the interconnection line is buried in the upper interlayer insulating layer,
wherein a line width of the upper part gradually decreases in a vertical direction away from the substrate, and
wherein a line width of the lower part gradually increases in the vertical direction away from the substrate,
wherein the second metal layer further comprises an etch stop layer between the lower interlayer insulating layer and the first metal laver, and
wherein the lower via portion is provided to penetrate the etch stop layer.