US 12,243,814 B2
Method of improving current balance of parallel chips in power module and power module employing same
Yu Cheol Park, Anyang-si (KR)
Assigned to Hyundai Mobis Co., Ltd., Seoul (KR)
Filed by HYUNDAI MOBIS Co., Ltd., Seoul (KR)
Filed on Jan. 13, 2022, as Appl. No. 17/574,993.
Prior Publication US 2023/0223330 A1, Jul. 13, 2023
Int. Cl. H01L 23/00 (2006.01); H01L 21/48 (2006.01); H01L 23/498 (2006.01); H01L 25/07 (2006.01)
CPC H01L 23/49844 (2013.01) [H01L 21/485 (2013.01); H01L 25/072 (2013.01); H01L 24/48 (2013.01); H01L 2224/48225 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A method of improving a current balance of parallel chips in a power module including plural power semiconductor chips connected to gate lines and source lines extending from gate pins and source pins in parallel by different distances, the method comprising:
forming a current area of each of a gate line and a source line connected to power semiconductor chips other than a first power semiconductor chip closest to the gate pin and the source pin larger than a current area of each of a gate line and a source line connected to the first power semiconductor chip in the power module.