US 12,243,812 B2
Alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages
Dae-Woo Kim, Phoenix, AZ (US); and Sujit Sharan, Chandler, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Nov. 3, 2023, as Appl. No. 18/386,913.
Application 18/386,913 is a division of application No. 16/219,765, filed on Dec. 13, 2018, granted, now 11,848,259.
Application 16/219,765 is a continuation of application No. 15/749,462, granted, now 10,177,083, issued on Jan. 8, 2019, previously published as PCT/US2015/058069, filed on Oct. 29, 2015.
Prior Publication US 2024/0071884 A1, Feb. 29, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 23/13 (2006.01); H01L 23/498 (2006.01); H01L 25/065 (2023.01); H01L 23/48 (2006.01)
CPC H01L 23/49827 (2013.01) [H01L 23/13 (2013.01); H01L 23/49822 (2013.01); H01L 23/5381 (2013.01); H01L 24/00 (2013.01); H01L 25/0655 (2013.01); H01L 23/48 (2013.01); H01L 24/16 (2013.01); H01L 24/17 (2013.01); H01L 2224/14 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16238 (2013.01); H01L 2224/1703 (2013.01); H01L 2224/171 (2013.01); H01L 2224/17133 (2013.01); H01L 2224/17177 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1435 (2013.01); H01L 2924/1517 (2013.01); H01L 2924/153 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A method of fabricating a plurality of silicon bridge dies, the method comprising:
providing a wafer having a plurality of silicon bridge dies thereon, each of the plurality of silicon bridge dies having an uppermost layer of copper pads exposed;
forming a silicon nitride layer on the wafer, the silicon nitride layer covering the uppermost layer of copper pads of the plurality of silicon bridge dies; and
singulating the plurality of silicon bridge dies by sawing along scribe lines of the wafer, through the silicon nitride layer.
 
6. A method of fabricating a semiconductor structure, the method comprising:
providing a substrate having a lower insulating layer disposed thereon, the substrate having a perimeter, the perimeter having a first side and a second side laterally opposite the first side from a cross-sectional perspective;
forming a metallization structure disposed on the lower insulating layer, the metallization structure comprising conductive routing disposed in a dielectric material stack;
forming a conductive pad disposed in a plane above the metallization structure, the conductive pad electrically coupled to the conductive routing of the metallization structure;
forming a conductive structure laterally adjacent to the metallization structure and the conductive pad, the conductive structure comprising a vertically dense arrangement of lines and vias aligned along a common axis; and
forming an upper insulating layer disposed on the conductive pad, the upper insulating layer having a perimeter substantially the same as the perimeter of the substrate, the upper insulating layer having a hole exposing only a portion of the conductive pad, and the upper insulating layer entirely covering the conductive structure, wherein an entirety of the upper insulating layer has a uniform thickness and is planar, and wherein the upper insulating layer is entirely within the first side and the second side of the perimeter from the cross-sectional perspective.