| CPC H01L 23/4827 (2013.01) [H01L 23/295 (2013.01); H01L 24/05 (2013.01); H01L 27/088 (2013.01); H01L 2224/05644 (2013.01); H01L 2224/05655 (2013.01); H01L 2924/10253 (2013.01)] | 17 Claims |

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1. A chip scale package (CSP) semiconductor device comprising:
a semiconductor substrate having a front surface and a back surface opposite the front surface of the semiconductor substrate;
a plurality of contact pads attached to the front surface of the semiconductor substrate;
a metal layer stack attached to the back surface of the semiconductor substrate, the metal layer stack comprising a first titanium layer;
a first nickel layer;
a silver layer;
a second nickel layer; and
a metallic layer comprising titanium; and
a compound layer attached to the metal layer stack;
wherein a thickness of the semiconductor substrate is less than or equal to 35 microns;
wherein the first titanium layer, the first nickel layer, the silver layer, the second nickel layer, and the metallic layer are in sequence;
wherein the compound layer comprises
a resin material; and
a filler material;
wherein a coefficient of thermal expansion of the compound layer is less than or equal to 9 ppm/° C.;
wherein a glass transition temperature of the compound layer is larger than 150° C.; and
wherein a bending strength of the semiconductor device measured by a three-point bending test with two-millimeter test span, at 25° C., is greater than or equal to 5 Newton per millimeter in width.
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