US 12,243,806 B2
Nested architectures for enhanced heterogeneous integration
Ravindranath Mahajan, Chandler, AZ (US); Debendra Mallik, Chandler, AZ (US); Sujit Sharan, Chandler, AZ (US); and Digvijay Raorane, Chandler, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 27, 2023, as Appl. No. 18/397,906.
Application 18/397,906 is a continuation of application No. 18/238,726, filed on Aug. 28, 2023.
Application 18/238,726 is a continuation of application No. 18/089,535, filed on Dec. 27, 2022, granted, now 11,742,261, issued on Aug. 29, 2023.
Application 18/089,535 is a continuation of application No. 16/291,314, filed on Mar. 4, 2019, granted, now 11,798,865, issued on Oct. 24, 2023.
Prior Publication US 2024/0128162 A1, Apr. 18, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/48 (2006.01); H01L 21/56 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/34 (2006.01); H01L 23/538 (2006.01); H01L 25/18 (2023.01)
CPC H01L 23/481 (2013.01) [H01L 21/565 (2013.01); H01L 21/76898 (2013.01); H01L 23/3128 (2013.01); H01L 23/315 (2013.01); H01L 23/34 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 24/09 (2013.01); H01L 24/17 (2013.01); H01L 24/29 (2013.01); H01L 24/73 (2013.01); H01L 25/18 (2013.01); H01L 2224/73253 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An electronic package, comprising:
a base substrate having a first side and a second side, the second side opposite the first side;
a component in a cavity of the base substrate, the component having a first side and a second side, the second side opposite the first side, and the component having a first sidewall and a second sidewall between the first side and the second side, the first sidewall laterally opposite the second sidewall;
a first plurality of through substrate vias in the base substrate, the first plurality of through substrate vias laterally spaced apart from the first sidewall of the component;
a second plurality of through substrate vias in the base substrate, the second plurality of through substrate vias laterally spaced apart from the second sidewall of the component;
a mold layer having a first portion laterally between the first plurality of through substrate vias and the first sidewall of the component, and a second portion laterally between the second plurality of through substrate vias and the second sidewall of the component, the mold layer in contact with the first side of the component, the first sidewall of the component, and the second sidewall of the component;
a redistribution layer on the first side of the base substrate, the redistribution layer vertically over the component, vertically over the mold layer, vertically over the first plurality of through substrate vias, and vertically over the second plurality of through substrate vias;
a first plurality of interconnects coupling the first side of the component to the redistribution layer;
a first die over a first portion of the redistribution layer, the first die over the first plurality of through substrate vias and over a first portion of the component;
a second plurality of interconnects coupling the first die to the first portion of the redistribution layer;
a second die over a second portion of the redistribution layer, the second die over the second plurality of through substrate vias and over a second portion of the component;
a third plurality of interconnects coupling the second die to the second portion of the redistribution layer; and
a plurality of bumps beneath the second side of the base substrate, the plurality of bumps vertically beneath the second side of the component, vertically beneath the first plurality of through substrate vias, and vertically beneath the second plurality of through substrate vias.