US 12,243,801 B2
Substrates for semiconductor device assemblies and systems with improved thermal performance and methods for making the same
Hyunsuk Chun, Boise, ID (US); Xiaopeng Qu, Boise, ID (US); and Chan H. Yoo, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jan. 13, 2023, as Appl. No. 18/154,615.
Application 18/154,615 is a continuation of application No. 17/061,435, filed on Oct. 1, 2020, granted, now 11,557,526.
Claims priority of provisional application 63/043,694, filed on Jun. 24, 2020.
Prior Publication US 2023/0154823 A1, May 18, 2023
Int. Cl. H01L 23/373 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/367 (2006.01); H01L 23/498 (2006.01)
CPC H01L 23/373 (2013.01) [H01L 23/367 (2013.01); H01L 23/498 (2013.01); H01L 24/16 (2013.01); H01L 21/481 (2013.01); H01L 2224/16227 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A semiconductor device assembly, comprising:
a package substrate including a top surface, a bottom surface, and outer surfaces between the top and bottom surfaces;
a semiconductor device disposed over the top surface of the package substrate, the semiconductor device configured to generate heat during operation; and
an encapsulant material at least partially encapsulating the package substrate and the semiconductor device,
wherein the package substrate includes a layer of thermally conductive material configured to thermally conduct the heat generated by the semiconductor device laterally outward toward the outer surfaces, and one or more thermal vias extending from the layer of thermally conductive material to the top surface, the bottom surface, or both,
wherein the layer of thermally conductive material extends continuously from one outermost edge of the package substrate to an opposing outermost edge of the package substrate.