US 12,243,797 B1
3D stack of split graphics processing logic dies
Amrita Mathuriya, Portland, OR (US); Christopher B. Wilkerson, Portland, OR (US); Rajeev Kumar Dokania, Beaverton, OR (US); Debo Olaosebikan, San Francisco, CA (US); and Sasikanth Manipatruni, Portland, OR (US)
Assigned to Kepler Computing Inc., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on Sep. 17, 2021, as Appl. No. 17/478,843.
Application 17/478,843 is a continuation of application No. 17/396,585, filed on Aug. 6, 2021, granted, now 11,791,233.
Int. Cl. H10B 53/20 (2023.01); H01L 23/367 (2006.01); H01L 23/48 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 25/10 (2006.01); G06N 20/00 (2019.01)
CPC H01L 23/3675 (2013.01) [H01L 23/481 (2013.01); H01L 23/49816 (2013.01); H01L 23/49833 (2013.01); H01L 23/49838 (2013.01); H01L 23/5385 (2013.01); H01L 23/5386 (2013.01); H01L 25/105 (2013.01); G06N 20/00 (2019.01); H01L 2924/14335 (2013.01); H01L 2924/1438 (2013.01); H01L 2924/1441 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first die comprising a load and store unit; and
a second die stacked on the first die, wherein the second die includes a vector math unit and a matrix math unit, wherein the load and store unit is to store data generated by the vector math unit and the matrix math unit.