US 12,243,784 B2
Silicon phosphide semiconductor device
Tzu-Ching Lin, Hsinchu (TW); and Tuoh Bin Ng, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 19, 2023, as Appl. No. 18/354,801.
Application 18/354,801 is a continuation of application No. 17/379,180, filed on Jul. 19, 2021, granted, now 11,749,567.
Application 17/379,180 is a continuation of application No. 16/427,981, filed on May 31, 2019, granted, now 11,069,578, issued on Jul. 20, 2021.
Prior Publication US 2023/0360974 A1, Nov. 9, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/8238 (2006.01); H01L 21/285 (2006.01); H01L 21/306 (2006.01); H01L 27/092 (2006.01); H01L 29/08 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 21/823821 (2013.01) [H01L 21/28518 (2013.01); H01L 21/306 (2013.01); H01L 21/823814 (2013.01); H01L 21/823828 (2013.01); H01L 21/823871 (2013.01); H01L 27/0924 (2013.01); H01L 29/0847 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first source/drain region in a first semiconductor fin, the first source/drain region comprising a first single continuous material extending from a bottom surface of the first source/drain region to above a top surface of the first semiconductor fin, the first single continuous material comprising SiP:C:As;
a gate over and along sidewalls of the first semiconductor fin;
a gate seal spacer on a sidewall of the gate; and
a gate spacer on a sidewall of the gate seal spacer, wherein the first source/drain region contacts a vertical sidewall of the gate seal spacer, and a top surface of the gate seal spacer, and a sidewall of the gate spacer.