US 12,243,782 B2
Local gate height tuning by CMP and dummy gate design
Ming-Chang Wen, Kaohsiung (TW); Chang-Yun Chang, Taipei (TW); Keng-Yao Chen, Hsinchu (TW); Chen-Yu Tai, Hsinchu (TW); and Yi-Ting Fu, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING C0., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Aug. 4, 2023, as Appl. No. 18/365,405.
Application 18/365,405 is a continuation of application No. 17/884,324, filed on Aug. 9, 2022, granted, now 11,817,354.
Application 17/884,324 is a continuation of application No. 17/125,299, filed on Dec. 17, 2020, granted, now 11,508,623, issued on Nov. 22, 2022.
Claims priority of provisional application 62/955,734, filed on Dec. 31, 2019.
Prior Publication US 2023/0386927 A1, Nov. 30, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/00 (2006.01); H01L 21/306 (2006.01); H01L 21/321 (2006.01); H01L 21/8234 (2006.01); H01L 29/66 (2006.01)
CPC H01L 21/82345 (2013.01) [H01L 21/30625 (2013.01); H01L 21/3212 (2013.01); H01L 21/823431 (2013.01); H01L 21/823456 (2013.01); H01L 29/66545 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a first metal gate stack in a dummy region of a semiconductor substrate and a second metal gate stack in an active device region of the semiconductor substrate, the first and second metal gate stacks being different in composition; and
performing a chemical mechanical polishing (CMP) process using a slurry including charged abrasive nanoparticles, wherein the charged abrasive nanoparticles include a first concentration in the active device region different from a second concentration in the dummy region.