US 12,243,779 B2
Semiconductor structure and method for manufacturing semiconductor structure
Shuangshuang Wu, Hefei (CN); and Tzung-Han Lee, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Mar. 8, 2022, as Appl. No. 17/689,000.
Application 17/689,000 is a continuation of application No. PCT/CN2021/120247, filed on Sep. 21, 2021.
Claims priority of application No. 202110500614.6 (CN), filed on May 8, 2021.
Prior Publication US 2022/0359291 A1, Nov. 10, 2022
Int. Cl. H01L 21/768 (2006.01); H01L 21/304 (2006.01); H01L 23/48 (2006.01)
CPC H01L 21/76898 (2013.01) [H01L 21/304 (2013.01); H01L 21/76831 (2013.01); H01L 21/76832 (2013.01); H01L 23/481 (2013.01)] 3 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a base comprising an array region and a peripheral region located on a periphery of the array region, the base comprises a substrate and a first dielectric layer located on an upper surface of the substrate;
a Through Silicon Via (TSV) located in the peripheral region, the TSV passes through the first dielectric layer, and partially extends into the substrate;
a liner layer at least located on a sidewall and a bottom of the TSV;
a conductive layer, located in the TSV and entirely filling the TSV, wherein the liner layer comprising a first polish-stop layer, a first dielectric filler layer, a second polish-stop layer and a second dielectric filler layer that are sequentially stacked onto one another in a direction from the substrate to the conductive layer, the first polish-stop layer extends to an upper surface of the first dielectric layer;
a plurality of device units arranged in an array are formed in the first dielectric layer in the array region;
an interconnection structure, the interconnection structure passes through the first dielectric layer, a bottom of the interconnection structure being in contact with the device units, an upper surface of the interconnection structure being flush with an upper surface of the first polish-stop layer;
a second dielectric layer, located on the upper surface of the first polish-stop layer, an upper surface of the liner layer and an upper surface of the conductive layer; and
a metal layer, located in the second dielectric layer and in contact with the device units and the conductive layer.