US 12,243,778 B2
Self-aligned semiconductor device contacts having widths less than minimum lithography limits
Mitsuru Soma, Higashimatsuyama (JP); Masahiro Shimbo, Ojiya (JP); Masaki Kuramae, Aizuwakamatsu (JP); and Kouhei Uchida, Aizu-wakamatsu (JP)
Assigned to SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Scottsdale, AZ (US)
Filed by SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Scottsdale, AZ (US)
Filed on Nov. 30, 2023, as Appl. No. 18/525,212.
Application 17/114,668 is a division of application No. 16/449,890, filed on Jun. 24, 2019, granted, now 10,892,188, issued on Jan. 12, 2021.
Application 18/525,212 is a continuation of application No. 17/114,668, filed on Dec. 8, 2020, granted, now 11,876,018.
Claims priority of provisional application 62/860,959, filed on Jun. 13, 2019.
Prior Publication US 2024/0178064 A1, May 30, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/768 (2006.01); H01L 21/265 (2006.01); H01L 21/308 (2006.01); H01L 21/3213 (2006.01); H01L 29/10 (2006.01); H01L 29/40 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 21/76897 (2013.01) [H01L 21/26586 (2013.01); H01L 21/3086 (2013.01); H01L 21/32139 (2013.01); H01L 29/401 (2013.01); H01L 29/41741 (2013.01); H01L 29/4236 (2013.01); H01L 29/66666 (2013.01); H01L 29/7827 (2013.01); H01L 29/105 (2013.01); H01L 29/7813 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate including a surface;
a gate electrode formed in a gate trench extending into the substrate from the surface;
a channel region adjacent to the gate electrode and including a non-uniform channel dopant profile;
a source region adjacent to the gate electrode between the surface and the channel region, the source region including a non-uniform source dopant profile;
an insulator layer formed above the substrate; and
a source contact extending through the insulator layer, the source contact including a width less than a minimum lithography limit for a processing capability.
 
12. A semiconductor device, comprising:
a gate electrode formed in a gate trench extending into a substrate from a surface of the substrate;
a channel region adjacent to the gate electrode and including a channel dopant profile;
a source region adjacent to the gate electrode between the surface and the channel region, the source region including a source dopant profile;
an insulator layer formed above the substrate; and
a source contact extending through the insulator layer, the source contact including a width less than a minimum lithography limit for a processing capability.