US 12,243,777 B2
Semiconductor device and method of manufacturing the same
Woojin Lee, Hwaseong-si (KR); Hoon Seok Seo, Suwon-si (KR); Sanghoon Ahn, Hwaseong-si (KR); and Kyu-Hee Han, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Nov. 16, 2023, as Appl. No. 18/510,732.
Application 18/510,732 is a continuation of application No. 18/079,998, filed on Dec. 13, 2022, granted, now 11,823,952.
Application 18/079,998 is a continuation of application No. 17/174,409, filed on Feb. 12, 2021, granted, now 11,569,128, issued on Jan. 11, 2023.
Application 17/174,409 is a continuation of application No. 16/411,439, filed on May 14, 2019, granted, now 10,943,824, issued on Feb. 17, 2021.
Claims priority of application No. 10-2018-0113152 (KR), filed on Sep. 20, 2018.
Prior Publication US 2024/0087956 A1, Mar. 14, 2024
Int. Cl. H01L 21/768 (2006.01); H01L 23/528 (2006.01)
CPC H01L 21/76897 (2013.01) [H01L 21/7682 (2013.01); H01L 21/76834 (2013.01); H01L 21/76843 (2013.01); H01L 21/76883 (2013.01); H01L 21/76885 (2013.01); H01L 23/5283 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device, the method comprising:
forming a sacrificial layer on a substrate;
forming a lower connection line in the sacrificial layer;
selectively forming a capping pattern on a top surface of the lower connection line;
replacing the sacrificial layer with a first interlayer dielectric layer; and
selectively removing the capping pattern to form a recess that exposes the top surface of the lower connection line.