US 12,243,776 B2
Method of making a three-dimensional memory device using composite hard masks for formation of deep via openings
Roshan Jayakhar Tirukkonda, Milpitas, CA (US); Senaka Kanakamedala, San Jose, CA (US); Raghuveer S. Makala, Campbell, CA (US); Rahul Sharangpani, Fremont, CA (US); Monica Titus, Santa Clara, CA (US); and Adarsh Rajashekhar, Santa Clara, CA (US)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by SANDISK TECHNOLOGIES LLC, Addison, TX (US)
Filed on Oct. 22, 2021, as Appl. No. 17/508,036.
Application 17/508,036 is a continuation in part of application No. 17/494,114, filed on Oct. 5, 2021.
Application 17/494,114 is a continuation in part of application No. 17/355,955, filed on Jun. 23, 2021, granted, now 11,972,954.
Application 17/355,955 is a continuation in part of application No. 17/136,471, filed on Dec. 29, 2020, granted, now 12,010,841.
Prior Publication US 2022/0208600 A1, Jun. 30, 2022
Int. Cl. H01L 21/768 (2006.01); H01L 21/306 (2006.01); H01L 21/308 (2006.01)
CPC H01L 21/7688 (2013.01) [H01L 21/30608 (2013.01); H01L 21/3081 (2013.01); H01L 21/76811 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor structure, comprising:
forming a source-level semiconductor layer over a substrate;
forming an alternating stack of first material layers and second material layers over the source-level semiconductor layer;
forming a hard mask layer over the alternating stack;
forming cavities in the hard mask layer;
forming via openings through the alternating stack by performing an anisotropic etch process that transfers a pattern of the cavities in the hard mask layer through the alternating stack;
forming a cladding liner on sidewalls of the cavities in the hard mask layer and on a top surface of the hard mask layer; and
vertically extending the via openings at least through the source-level semiconductor layer by performing an additional anisotropic etch process employing a combination of the cladding liner and the hard mask layer as an etch mask.