CPC H01F 41/045 (2013.01) [H01F 17/0006 (2013.01); H01F 41/042 (2013.01); H01L 23/5227 (2013.01); H01L 23/5256 (2013.01); H01F 2017/0046 (2013.01); Y10T 29/4902 (2015.01)] | 20 Claims |
1. A method of manufacturing a semiconductor device, the method comprising:
forming a first conductive turn in physical contact with a first via and a second via; and
forming a second conductive turn in physical contact with a third via and a fourth via, wherein the first conductive turn and the second conductive turn are individually connected to two fuses, wherein a first one of the two fuses is misaligned from a second one of the two fuses, wherein the first via is adjacent to a first plurality of vias in physical contact with the first conductive turn, wherein the second via is adjacent to a second plurality of vias in physical contact with the first conductive turn, and wherein the third via is adjacent to a third plurality of vias in physical contact with the second conductive turn.
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