US 12,243,622 B2
Dynamic power management for on-chip memory
Edward Martin McCombs, Jr., Austin, TX (US)
Assigned to Arm Limited, Cambridge (GB)
Filed by Arm Limited, Cambridge (GB)
Filed on Aug. 11, 2022, as Appl. No. 17/885,753.
Prior Publication US 2024/0055035 A1, Feb. 15, 2024
Int. Cl. G11C 8/08 (2006.01); G06F 1/3234 (2019.01); G11C 5/14 (2006.01); G11C 8/10 (2006.01); G11C 8/12 (2006.01); G11C 8/14 (2006.01); G11C 8/18 (2006.01); G11C 11/4072 (2006.01); G11C 11/408 (2006.01)
CPC G11C 8/08 (2013.01) [G06F 1/3275 (2013.01); G11C 5/14 (2013.01); G11C 8/10 (2013.01); G11C 8/12 (2013.01); G11C 8/14 (2013.01); G11C 8/18 (2013.01); G11C 11/4072 (2013.01); G11C 11/4085 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A method for managing power in a memory, comprising:
receiving an access request for a memory, the access request including an address, the memory including a plurality of wordline sections, each wordline section including a number of wordlines;
applying power to control circuitry;
decoding the address, including:
determining, based on the address, an associated wordline, and
determining, based on the associated wordline, an associated wordline section; and
applying power to wordline control circuitry coupled to the associated wordline section, each wordline section of the plurality of wordline sections being coupled to a different wordline control circuitry, further including while applying power to the wordline control circuitry coupled to the associated wordline section, applying power to wordline control circuitry coupled to a different wordline section and applying power to input/output (I/O) circuitry.