US 12,243,621 B2
Buffer control of multiple memory banks
Shih-Lien Linus Lu, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Nov. 21, 2023, as Appl. No. 18/516,143.
Application 18/516,143 is a continuation of application No. 17/876,142, filed on Jul. 28, 2022, granted, now 11,862,292.
Application 17/876,142 is a continuation of application No. 17/345,911, filed on Jun. 11, 2021, granted, now 11,437,081, issued on Sep. 6, 2022.
Application 17/345,911 is a continuation of application No. 16/991,614, filed on Aug. 12, 2020, granted, now 11,043,250, issued on Jun. 22, 2021.
Prior Publication US 2024/0087624 A1, Mar. 14, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 7/22 (2006.01); G11C 7/10 (2006.01)
CPC G11C 7/222 (2013.01) [G11C 7/1036 (2013.01); G11C 7/1057 (2013.01); G11C 7/1084 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a first register configured to store an address of a corresponding one of a plurality of memory banks;
a second register indicating a first entry, wherein the first entry is configured to store an address of one of the memory banks, on which a write process is predicted to be completed next among the plurality of memory banks; and
a third register indicating a second entry to be updated.