US 12,243,619 B2
Memory array structure
Hung-Li Chiang, Taipei (TW); Jer-Fu Wang, Taipei (TW); Tzu-Chiang Chen, Hsinchu (TW); and Meng-Fan Chang, Taichung (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu (TW)
Filed on Jul. 12, 2022, as Appl. No. 17/863,201.
Prior Publication US 2024/0021226 A1, Jan. 18, 2024
Int. Cl. H03M 1/12 (2006.01); G11C 7/10 (2006.01); G11C 7/16 (2006.01); G11C 13/00 (2006.01)
CPC G11C 7/16 (2013.01) [G11C 7/1006 (2013.01); G11C 13/003 (2013.01); G11C 2213/77 (2013.01); H03M 1/12 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory array structure, comprising:
a word array, storing an N-bit word and comprising:
a plurality of first memory structures, wherein each first memory structure comprises a first transistor and a first memory element; and
a plurality of second memory structures, wherein each second memory structure comprises a second transistor and a plurality of second memory elements, each second memory element comprises a first end and a second end, the first end of each second memory element is coupled to a corresponding bit line, and the second end of each second memory element is coupled to a first end of the second transistor,
wherein each second memory structure further comprises a plurality of selectors, and each selector is coupled between the second end of the corresponding second memory element and the first end of the second transistor.