US 12,243,618 B2
Method of manufacturing semiconductor device
Meng-Sheng Chang, Hsinchu County (TW); Yao-Jen Yang, Hsinchu County (TW); Yih Wang, Hsinchu (TW); and Fu-An Wu, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on Feb. 3, 2023, as Appl. No. 18/164,274.
Application 18/164,274 is a continuation of application No. 16/713,967, filed on Dec. 13, 2019, granted, now 11,600,626.
Prior Publication US 2023/0189512 A1, Jun. 15, 2023
Int. Cl. G11C 7/10 (2006.01); G11C 5/06 (2006.01); G11C 8/08 (2006.01); G11C 17/16 (2006.01); G11C 17/18 (2006.01); H01L 23/522 (2006.01); H01L 23/525 (2006.01); H10B 20/25 (2023.01)
CPC G11C 7/1096 (2013.01) [G11C 5/063 (2013.01); G11C 7/1069 (2013.01); G11C 8/08 (2013.01); G11C 17/165 (2013.01); G11C 17/18 (2013.01); H01L 23/5226 (2013.01); H01L 23/5252 (2013.01); H10B 20/25 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
coupling a first gate to a first word line through a first gate via, wherein the first gate extends along a first direction;
coupling a second gate to a second word line through a second gate via, wherein each of the first gate via and the second gate via and each of the corresponding parts of the first and second gates is disposed on a first active area which extends along a second direction, wherein the second gate extends along the first direction and is separated from the first gate along the second direction;
coupling the first active area to a first bit line through a first conductive via; and
aligning the first gate via, the second gate via and the first conductive via with each other along the second direction.