US 12,243,617 B2
Loopback circuit for low-power memory devices
Yoshihito Morishita, Shibuya-ku (JP)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Oct. 31, 2022, as Appl. No. 18/051,143.
Prior Publication US 2024/0144984 A1, May 2, 2024
Int. Cl. G11C 7/10 (2006.01); G11C 7/22 (2006.01)
CPC G11C 7/1084 (2013.01) [G11C 7/1057 (2013.01); G11C 7/22 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A device comprising:
a first data input (DQ) circuitry comprising an input buffer configured to generate a loopback data signal based at least in part on a data signal received at the first DQ circuitry when the device operates in a loopback mode, wherein the loopback mode comprises a command bus training mode of the device;
a second DQ circuitry comprising an output buffer configured to receive the loopback data signal from the first DQ circuitry and to output the loopback data signal via a data pin; and
a mode register used to receive an indication, from a host device, to set the device in the loopback mode and to indicate a target for monitoring in the loopback mode.