US 12,243,614 B2
Single ended sense amplifier with current pulse circuit
Siva Kumar Chinthu, Bangalore (IN); Suresh Pasupula, Bangalore (IN); Devesh Dwivedi, Bangalore (IN); and Chunsung Chiang, San Jose, CA (US)
Assigned to GlobalFoundries U.S. Inc., Malta, NY (US)
Filed by GlobalFoundries U.S. Inc., Malta, NY (US)
Filed on Oct. 17, 2022, as Appl. No. 18/046,961.
Prior Publication US 2024/0127868 A1, Apr. 18, 2024
Int. Cl. G11C 7/06 (2006.01); G11C 7/10 (2006.01); G11C 7/12 (2006.01)
CPC G11C 7/067 (2013.01) [G11C 7/109 (2013.01); G11C 7/12 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A memory circuit, comprising:
a bit cell having a resistor configurable to a low resistive state and a high resistive state;
a p-type metal-oxide semiconductor (PMOS) transistor having a drain connected to a data path of the bit cell; and
a NAND gate having an output coupled to a gate of the PMOS device, wherein a first input of the NAND gate is controlled by a state of the bit cell;
wherein the memory circuit is embodied in one of a resistive random access memory (RRAM) or a Magnetoresistive random-access memory (MRAM).