US 12,243,610 B2
Memory with parallel main and test interfaces
James Brian Johnson, Boise, ID (US); Kunal R. Parekh, Boise, ID (US); Brent Keeth, Boise, ID (US); Eiichi Nakano, Boise, ID (US); and Amy Rae Griffin, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 23, 2022, as Appl. No. 17/821,676.
Prior Publication US 2024/0071556 A1, Feb. 29, 2024
Int. Cl. G11C 29/00 (2006.01); G11C 7/10 (2006.01); G11C 29/56 (2006.01)
CPC G11C 29/56004 (2013.01) [G11C 7/1039 (2013.01); G11C 29/56016 (2013.01); G11C 2029/5602 (2013.01)] 12 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a set of one or more memory arrays of a first memory die;
a set of one or more first contacts of the first memory die that are configured for communicative coupling, during assembly of the apparatus, with a set of one or more contacts of a second memory die, at least a subset of the set of one or more first contacts coupled with a first data bus of the first memory die; and
a set of one or more second contacts of the first memory die that are configured for pre-assembly testing operations of the first memory die, wherein the pre-assembly testing operations occur before the assembly of the apparatus comprising the communicative coupling of the set of one or more first contacts of the first memory die with the set of one or more contacts of the second memory die, wherein at least a subset of the set of one or more second contacts coupled with one or more second data buses of the first memory die, and wherein the set of one or more second contacts of the first memory die is electrically isolated from circuitry of the second memory die and the set of one or more second contacts of the first memory die is in contact with a dielectric portion of the second memory die based at least in part on the assembly of the apparatus comprising the communicative coupling.