| CPC G11C 29/50012 (2013.01) [G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/16 (2013.01)] | 15 Claims |
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1. A non-volatile memory device, comprising:
a memory cell array comprising M word lines and N bit lines;
a control logic device, configured to receive an external signal, and output an octo signal, a program signal and an erase signal;
an address decoder, configured to receive the octo signal, and output a word line selection signal and a bit line selection signal;
a high voltage generator, configured to receive the program signal and the erase signal, and output a read voltage and a write voltage;
a row decoder, configured to receive the word line selection signal, and select a word line of the memory cell array;
a column decoder, configured to receive the bit line selection signal, and select a bit line of the memory cell array;
a page buffer, configured to receive the read voltage and the write voltage, and save data to be programmed; and
a data latch, configured to save read data obtained from a read operation;
wherein the non-volatile memory device is configured to simultaneously select non-contiguous word lines that are located every eighth word line among the M word lines and correspond to octo rows in response to the octo signal being applied to the address decoder,
wherein a write voltage is configured to be applied to memory cells connected to the word lines corresponding to the octo rows, and
wherein a voltage that is different from the write voltage is configured to be applied to memory cells connected to word lines, except for the word lines corresponding to the octo-rows.
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