US 12,243,607 B2
Indicating a status of a memory built-in self-test
Scott E. Schaefer, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 21, 2023, as Appl. No. 18/392,487.
Application 18/392,487 is a continuation of application No. 17/807,625, filed on Jun. 17, 2022, granted, now 11,929,134.
Prior Publication US 2024/0127902 A1, Apr. 18, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 29/46 (2006.01); G11C 7/10 (2006.01); G11C 29/12 (2006.01); G11C 29/44 (2006.01)
CPC G11C 29/46 (2013.01) [G11C 7/1009 (2013.01); G11C 29/12005 (2013.01); G11C 29/4401 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a first mode register configured to store one or more bits indicating whether a memory built-in self-test is enabled;
a pin configured to be in a state selected from a first state and a second state, wherein:
the state of the pin indicates a status associated with the memory built-in self-test while the memory built-in self-test is enabled, and
the state of the pin indicates a status associated with a function of the memory device while the memory built-in self-test is disabled; and
a controller configured to set the pin to the first state or the second state based on whether the one or more bits identify that the memory built-in self-test is enabled.