US 12,243,606 B2
Semiconductor device, memory system and method of controlling semiconductor device thereof
Hsin-Nan Chueh, Hsinchu County (TW); Wenliang Chen, Hsinchu County (TW); and Chin-Hung Liu, Hsinchu County (TW)
Assigned to AP MEMORY TECHNOLOGY CORPORATION, Hsinchu County (TW)
Filed by AP MEMORY TECHNOLOGY CORPORATION, Hsinchu County (TW)
Filed on Sep. 23, 2021, as Appl. No. 17/483,508.
Claims priority of provisional application 63/132,484, filed on Dec. 31, 2020.
Prior Publication US 2022/0208295 A1, Jun. 30, 2022
Int. Cl. G11C 29/44 (2006.01); G06F 11/16 (2006.01); G11C 29/42 (2006.01); H01L 23/00 (2006.01)
CPC G11C 29/4401 (2013.01) [G06F 11/1666 (2013.01); G11C 29/42 (2013.01); H01L 24/14 (2013.01); G11C 2029/4402 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/15311 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first memory die including a first memory space and a second memory space;
a second memory die different from the first memory die, and the second memory die including a third memory space and a fourth memory space;
a non-volatile memory circuit configured to store a first repair table file corresponding to the first memory space and a second repair table file corresponding to the third memory space; and
a logic die coupled to the first memory die and the non-volatile memory circuit, the logic die configured to select one of the first repair table file and the second repair table file as a selected repair table file according to an input address, and to selectively access the second memory space or the first memory space of the first memory die or selectively access the third memory space or the fourth memory space of the second memory die according to a comparing result of the input address and the selected repair table file;
wherein the first memory die is different from the logic die, and the non-volatile memory circuit is not disposed in the first memory die.