US 12,243,604 B1
Scannable memory array and a method for scanning memory
Thomas Ziaja, Austin, TX (US); and Paul Jordan, Austin, TX (US)
Assigned to SambaNova Systems, Inc., Palo Alto, CA (US)
Filed by SambaNova Systems, Inc., Palo Alto, CA (US)
Filed on Jun. 24, 2024, as Appl. No. 18/752,634.
Claims priority of provisional application 63/569,722, filed on Mar. 25, 2024.
Int. Cl. G11C 29/12 (2006.01); G11C 29/10 (2006.01)
CPC G11C 29/12015 (2013.01) [G11C 29/10 (2013.01)] 22 Claims
OG exemplary drawing
 
1. An array of memory cells, comprising:
a scan chain including a first chain segment that includes N memory cells of the array of memory cells;
wherein;
N is an integer number greater than 1;
the first chain segment is configured to receive a sequence of non-overlapping sub-clock pulses from a sequence generator, wherein the sequence generator has a scan clock input (an SCLK input) and at least N−1 scan sub-clock outputs;
each of the at least N−1 scan sub-clock outputs is coupled with one of the N memory cells;
upon receiving a pulse in a signal on the SCLK input, the sequence generator generates the sequence of non-overlapping sub-clock pulses and outputs the non-overlapping sub-clock pulses on respective individual scan sub-clock outputs of the at least N−1 scan sub-clock outputs; and
a total duration of the sequence of non-overlapping sub-clock pulses is equal to or less than a total duration of a cycle of the signal on the SCLK input.