US 12,243,603 B2
At-speed test of functional memory interface logic in devices
Devanathan Varadarajan, Allen, TX (US); and Lei Wu, Sugar Land, TX (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Dec. 21, 2023, as Appl. No. 18/392,740.
Application 17/364,647 is a division of application No. 16/192,796, filed on Nov. 15, 2018, granted, now 11,087,857.
Application 18/392,740 is a continuation of application No. 17/364,647, filed on Jun. 30, 2021, abandoned.
Claims priority of provisional application 62/586,614, filed on Nov. 15, 2017.
Prior Publication US 2024/0120016 A1, Apr. 11, 2024
Int. Cl. G11C 29/12 (2006.01); G01R 31/3185 (2006.01); G11C 29/02 (2006.01); G11C 29/10 (2006.01); G11C 29/14 (2006.01); G11C 29/16 (2006.01); G11C 29/26 (2006.01); G11C 29/32 (2006.01); G11C 29/36 (2006.01)
CPC G11C 29/12015 (2013.01) [G01R 31/318594 (2013.01); G01R 31/318597 (2013.01); G11C 29/022 (2013.01); G11C 29/023 (2013.01); G11C 29/10 (2013.01); G11C 29/1201 (2013.01); G11C 29/14 (2013.01); G11C 29/16 (2013.01); G11C 29/26 (2013.01); G11C 29/32 (2013.01); G11C 29/36 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A method comprising:
providing a test sequence to a first input of a first multiplexer, the first multiplexer comprising a second input coupled to an output of a functional memory interface circuit, an output coupled to a first memory, and a selection input;
controlling the selection input of the first multiplexer with a mode control circuit that comprises a second multiplexer having an output coupled to the selection input of the first multiplexer, a first input coupled to an output of a first flip-flop, and a second input coupled to an output of a second flip-flop;
during a built-in-self-test (BIST) mode,
controlling the selection input of the first multiplexer with the output of the first flip-flop, and
providing a clock signal with a clock control circuit with a slow-speed; and
during a functional test mode,
controlling the selection input of the first multiplexer with the output of the second flip-flop, and
providing the clock signal with the clock control circuit with a fast-speed that is faster than the slow-speed.