US 12,243,602 B2
Method, device, and circuit for high-speed memories
Jaspal Singh Shah, Ottawa (CA); and Atul Katoch, Kanata (CA)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jan. 12, 2024, as Appl. No. 18/411,822.
Application 18/411,822 is a continuation of application No. 17/834,122, filed on Jun. 7, 2022, granted, now 11,894,086.
Claims priority of provisional application 63/303,638, filed on Jan. 27, 2022.
Prior Publication US 2024/0153573 A1, May 9, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 29/12 (2006.01); G11C 29/36 (2006.01); G11C 29/46 (2006.01)
CPC G11C 29/1201 (2013.01) [G11C 29/12015 (2013.01); G11C 29/36 (2013.01); G11C 29/46 (2013.01); G11C 2029/3602 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A control circuit, comprising:
a first clock generator configured to generate a mission mode clock (MDCK) signal according to an input clock signal and a chip enable (CE) signal; and
a second clock generator configured to generate a design for testability (DFT) mode clock (DDCK) signal according to the input clock signal and provide the first clock generator with a DFT enable (DFTEN) signal;
wherein in response to the DFTEN signal being in a high logic state, an output clock signal, provided by the control circuit, follows the DDCK signal, and in response to the DFTEN signal being in a low logic state, the output clock signal follows the MDCK signal.