CPC G11C 29/1201 (2013.01) [G11C 29/12015 (2013.01); G11C 29/36 (2013.01); G11C 29/46 (2013.01); G11C 2029/3602 (2013.01)] | 20 Claims |
1. A control circuit, comprising:
a first clock generator configured to generate a mission mode clock (MDCK) signal according to an input clock signal and a chip enable (CE) signal; and
a second clock generator configured to generate a design for testability (DFT) mode clock (DDCK) signal according to the input clock signal and provide the first clock generator with a DFT enable (DFTEN) signal;
wherein in response to the DFTEN signal being in a high logic state, an output clock signal, provided by the control circuit, follows the DDCK signal, and in response to the DFTEN signal being in a low logic state, the output clock signal follows the MDCK signal.
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