US 12,243,596 B2
Flash memory device and program method thereof using leakage current compensation
Wen-Chiao Ho, Taichung (TW)
Assigned to Winbond Electronics Corp., Taichung (TW)
Filed by Winbond Electronics Corp., Taichung (TW)
Filed on Nov. 6, 2022, as Appl. No. 17/981,462.
Prior Publication US 2024/0153569 A1, May 9, 2024
Int. Cl. G11C 16/14 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/24 (2006.01); G11C 16/28 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/3459 (2013.01) [G11C 16/102 (2013.01); G11C 16/24 (2013.01); G11C 16/28 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A flash memory device, comprising:
a memory array comprising a first memory block, wherein the first memory block comprises a plurality of first memory cells;
a first global bit line coupled to the first memory cells; and
a sense amplifying device coupled to the first global bit line, wherein in a leakage current detection operation, the sense amplifying device detects a leakage current generated by the first memory cells on the first global bit line to obtain leakage current simulation information,
wherein in a program operation, the sense amplifying device provides a reference current according to the leakage current simulation information and compares a sensing current generated by a selected memory cell in the first memory cells on the first global bit line with the reference current to perform a program verification,
wherein the sense amplifying device comprises:
a first sense amplifier having a first input terminal coupled to the first global bit line; and
a ratio controller coupled to a second input terminal of the first sense amplifier, wherein the ratio controller receives a test current, and in the leakage current detection operation, adjusts the test current according to a setting ratio to generate a replica leakage current.