US 12,243,593 B2
Low power read method and a memory device capable thereof
Xiang Yang, Santa Clara, CA (US); Deepanshu Dutta, Fremont, CA (US); Ohwon Kwon, Milpitas, CA (US); James Kai, Fremont, CA (US); and Yuki Mizutani, Milpitas, CA (US)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by SanDisk Technologies LLC, Addison, TX (US)
Filed on Mar. 3, 2022, as Appl. No. 17/685,613.
Prior Publication US 2023/0282288 A1, Sep. 7, 2023
Int. Cl. G11C 16/24 (2006.01); G11C 16/04 (2006.01); G11C 16/26 (2006.01); G11C 16/08 (2006.01)
CPC G11C 16/26 (2013.01) [G11C 16/0483 (2013.01); G11C 16/24 (2013.01); G11C 16/08 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a chip including circuitry and a plurality of memory blocks containing an array of memory cells and a plurality of bit lines, the circuitry overlying or underlying the array of memory cells;
the bit lines of the memory blocks being divided into first and second portions that are electrically connected with one another via at least one transistor so that at least one of the first and second portions of each bit line can be charged independently of the other portion of the same bit line; and
a controller configured to
receive a command to sense data from the chip,
determine whether the data can be sensed from the chip by charging only the first portion,
in response to a determination that the data can be sensed by charging only the first portion, put the at least one transistor in an off condition so only the first portion of at least some of the bit lines is charged during a sensing operation, and
in response to a determination that the data cannot be sensed by charging only the first portion, put the at least one transistor in an on condition so that both the first and second portions of each bit line are charged,
wherein the first portions are located on one side of the at least one transistor and the second portions are located on an opposite side of the at least one transistor, and
wherein (i) the circuitry includes a plurality of sense amplifiers that are in electrical communication with the bit lines, (ii) some of the sense amplifiers are electrically connected with the first portions of one or more of the plurality of bit lines, and (iii) others of the sense amplifiers are electrically connected with the second portions of one or more of the plurality of bit lines.