US 12,243,592 B2
One time programmable memory
Yu-Der Chih, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on May 15, 2023, as Appl. No. 18/317,665.
Application 18/317,665 is a continuation of application No. 17/693,908, filed on Mar. 14, 2022, granted, now 11,651,826.
Application 17/693,908 is a continuation of application No. 16/901,200, filed on Jun. 15, 2020, granted, now 11,276,469.
Prior Publication US 2023/0282287 A1, Sep. 7, 2023
Int. Cl. G11C 16/10 (2006.01); G11C 7/06 (2006.01); G11C 7/10 (2006.01); G11C 16/04 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01); G11C 17/08 (2006.01)
CPC G11C 16/24 (2013.01) [G11C 7/06 (2013.01); G11C 7/1063 (2013.01); G11C 16/0441 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 17/08 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a first transistor;
a second transistor connected in series with the first transistor, wherein the second transistor is programmable between a first state and a second state;
a bit line connected to the second transistor;
a sense amplifier connected to the bit line, wherein the sense amplifier is operative to sense data from the bit line; and
a feedback circuit connected between an output of the sense amplifier and the bit line, wherein the feedback circuit is operative to suppress a bit line current of the bit line in response to the sense amplifier sensing a first value from the first transistor.