US 12,243,591 B2
In-place write techniques without erase in a memory device
Xiang Yang, Santa Clara, CA (US); Jiacen Guo, Cupertino, CA (US); and Takayuki Inoue, Fujisawa (JP)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by SanDisk Technologies LLC, Addison, TX (US)
Filed on Aug. 26, 2022, as Appl. No. 17/896,587.
Prior Publication US 2024/0071508 A1, Feb. 29, 2024
Int. Cl. G11C 7/00 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/14 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/102 (2013.01) [G11C 16/08 (2013.01); G11C 16/14 (2013.01); G11C 16/3459 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of programming a memory device, comprising the steps of:
preparing a plurality of memory blocks, the memory blocks including an array of memory cells that can be programmed to retain one or more bits of data per memory cell;
receiving a data write instruction;
programming the memory cells of the memory blocks to a one bit per memory cell (SLC) format that includes a first SLC data state and a second SLC data state; and
in response to the data programmed to the memory cells of the memory blocks in the SLC format reaching an SLC limit prior to completion of the data write instruction, without erasing the memory cells programmed to the SLC format, programming the memory cells of at least some of the plurality of memory blocks from the SLC format to a two bits per memory cell (MLC) format, and
wherein the step of programming the memory cells from the SLC format to the MLC format includes inhibiting at least some of the memory cells in the first SLC data state to form a first MLC data state, programming at least some of the memory cells in the first SLC data state to form a second MLC data state, programming at least some of the memory cells in the second SLC data state to form a third MLC data state, and programming at least some of the memory cells in the second SLC data state to form a fourth MLC data state.