US 12,243,590 B2
Method and apparatus for improving write uniformity in a memory device
Shantanu R. Rajwade, San Mateo, CA (US); Christian Mion, Cupertino, CA (US); Pranav Kalavade, San Jose, CA (US); Rohit S. Shenoy, Fremont, CA (US); Xin Sun, Fremont, CA (US); and Kristopher Gaewsky, El Dorado Hills, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Nov. 17, 2021, as Appl. No. 17/528,892.
Prior Publication US 2023/0154539 A1, May 18, 2023
Int. Cl. G06F 3/06 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01); G11C 11/56 (2006.01)
CPC G11C 16/10 (2013.01) [G06F 3/061 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G11C 16/0483 (2013.01); G11C 16/26 (2013.01); G11C 16/3459 (2013.01); G11C 11/56 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a memory comprising a group of memory cells coupled to a wordline; and
a controller configured to:
program one or more lower pages of the group of memory cells responsive to a sequential write operation;
skip programming of one or more upper pages of the group of memory cells responsive to the sequential write operation; and
program the one or more upper pages of the group of memory cells responsive to one or more random write commands.