US 12,243,589 B2
Memory device and method for operating the same
Pei-Chun Liao, Hsinchu County (TW); Yu-Kai Chang, Hsinchu (TW); Yi-Ching Liu, Hsinchu (TW); Yu-Ming Lin, Hsinchu (TW); Yih Wang, Hsinchu (TW); and Chieh Lee, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Aug. 30, 2022, as Appl. No. 17/898,733.
Prior Publication US 2024/0071504 A1, Feb. 29, 2024
Int. Cl. G11C 16/26 (2006.01); G11C 16/08 (2006.01); G11C 16/32 (2006.01)
CPC G11C 16/08 (2013.01) [G11C 16/26 (2013.01); G11C 16/32 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a memory array comprising a plurality of memory cells, wherein each one of the plurality of memory cells is coupled to a control line, a data line, and a source line and, during a normal operation, is configured to receive a first voltage signal through the control line and to receive a second voltage signal through at least one of the data line or the source line,
wherein the first voltage signal oscillates between a first voltage level and a second voltage level lower than the first voltage level;
a driver circuit coupled to the plurality of memory cells and configured to output at least one of the first voltage signal or the second voltage signal to each one of the plurality of memory cells, wherein the driver circuit comprises:
at least one of a header unit that is configured to generate a first reference voltage signal, or a footer unit that is configured to generate a second reference voltage signal; and
a transmission unit coupled in series with the at least one of the header unit or the footer unit and coupled to a portion of the plurality of memory cells, wherein the transmission unit is configured to transmit the first reference voltage signal or the second reference voltage signal as the first voltage signal, to the portion of the plurality of memory cells; and
a recover circuit configured to output, during a recover operation, a third voltage signal, through the driver circuit to at least one of the plurality of memory cells, wherein the third voltage signal is configured to have a highest voltage level higher than the first voltage level and a lowest voltage level equal to the second voltage level.