	US 12,243,587 B2
	Multiple row programming operation in artificial neural network array
Hieu Van Tran, San Jose, CA (US); Stephen Trinh, San Jose, CA (US); Stanley Hong, San Jose, CA (US); Thuan Vu, San Jose, CA (US); Anh Ly, San Jose, CA (US); and Fan Luo, Fremont, CA (US)
Assigned to SILICON STORAGE TECHNOLOGY, INC., San Jose, CA (US)
Filed by Silicon Storage Technology, Inc., San Jose, CA (US)
Filed on Dec. 6, 2022, as Appl. No. 18/076,129.
Claims priority of provisional application 63/409,177, filed on Sep. 22, 2022.
Prior Publication US 2024/0112729 A1, Apr. 4, 2024
Int. Cl. G11C 11/56 (2006.01); G06N 3/04 (2023.01); G11C 16/10 (2006.01)

CPC G11C 11/5628 (2013.01) [G06N 3/04 (2013.01); G11C 11/5671 (2013.01); G11C 16/10 (2013.01); G11C 2216/04 (2013.01)]

15 Claims

1. A method comprising:

ramping up an output of a high voltage generator to a first voltage level;

while maintaining the output of the high voltage generator at the first voltage level, programming a plurality of words of K rows of memory cells in an array of memory cells using the output of the high voltage generator, where K>1;

after the programming, ramping down the output of the high voltage generator to a second voltage level; and

for one or more of the K rows, ramping up a control gate line voltage to a third voltage level prior to programming the row and ramping down the control gate line voltage to a fourth voltage level after programming the row, wherein the fourth voltage level equals the second voltage level.