US 12,243,585 B1
Memory write assist
M Sultan M Siddiqui, Noida (IN); Md Amir Arif, New Delhi (IN); Tejaswini Saini, Uttam Nagar (IN); Sudhir Kumar, Shastri Nagar (IN); and Ravindra Shrivastava, Noida (IN)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Feb. 14, 2023, as Appl. No. 18/168,847.
Int. Cl. G11C 11/24 (2006.01); G11C 11/419 (2006.01)
CPC G11C 11/419 (2013.01) 20 Claims
OG exemplary drawing
 
1. A circuit, comprising:
a dynamic complementary metal-oxide-semiconductor (CMOS) inverter level translator circuit,
wherein the dynamic CMOS inverter level translator circuit is electrically connected to a first power domain,
wherein the dynamic CMOS inverter level translator circuit has a first input node configured to receive a first trigger signal generated in the first power domain, and
wherein the dynamic CMOS inverter level translator circuit has a second input node configured to receive a second trigger signal generated in a second power domain different from the first power domain; and
a first capacitor that is electrically coupled to an output node of the dynamic CMOS inverter level translator circuit,
wherein the first capacitor selectively charges to the first power domain through the dynamic CMOS inverter level translator circuit based on the first trigger signal, and
wherein the first capacitor selectively discharges to provide a negative coupling voltage to a write assist supply node, the write assist supply node being electrically coupled to a negative supply node of a bit line driver circuit of a memory array.