US 12,243,584 B2
In-memory compute array with integrated bias elements
Anuj Grover, New Delhi (IN); Tanmoy Roy, Grenoble (FR); and Nitin Chawla, Noida (IN)
Assigned to STMicroelectronics International N. V., Geneva (CH)
Filed by STMicroelectronics International N.V., Geneva (CH)
Filed on Feb. 10, 2023, as Appl. No. 18/167,580.
Application 18/167,580 is a continuation of application No. 17/375,945, filed on Jul. 14, 2021, granted, now 11,605,424.
Application 17/375,945 is a continuation of application No. 16/882,024, filed on May 22, 2020, granted, now 11,094,376, issued on Aug. 17, 2021.
Claims priority of provisional application 62/858,265, filed on Jun. 6, 2019.
Prior Publication US 2023/0186983 A1, Jun. 15, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/41 (2006.01); G11C 11/419 (2006.01); H10B 10/00 (2023.01)
CPC G11C 11/419 (2013.01) [H10B 10/12 (2023.02)] 20 Claims
OG exemplary drawing
 
10. A system, comprising:
data processing means; and
in-memory computing (IMC) means coupled to the data processing means, wherein the IMC means, in operation:
stores a plurality of values in respective memory bitcells of a first plurality of bitcells arranged as a plurality of rows of bitcells intersecting a plurality of columns of bitcells, each bitcell of the first plurality of bitcells identifiable by a corresponding row and column;
performs a plurality of IMC operations, each of the IMC operations using one or more of the stored plurality of values as an operand;
stores results of the plurality of IMC operations in a second plurality of bitcells, the second plurality of bitcells being formed from bitcells of the first plurality of bitcells; and
computationally combines results of the plurality of IMC operations with respective bias values.