US 12,243,582 B2
Semiconductor integrated circuit
Eikichi Shimizu, Yokohama (JP)
Assigned to LAPIS Technology Co., Ltd., Yokohama (JP)
Filed by LAPIS Technology Co., Ltd., Yokohama (JP)
Filed on Mar. 28, 2023, as Appl. No. 18/190,980.
Claims priority of application No. 2022-057746 (JP), filed on Mar. 30, 2022.
Prior Publication US 2023/0317147 A1, Oct. 5, 2023
Int. Cl. G11C 11/413 (2006.01); G06F 1/3287 (2019.01); G06F 1/3293 (2019.01); G11C 5/14 (2006.01); H10B 10/00 (2023.01)
CPC G11C 11/413 (2013.01) [G06F 1/3287 (2013.01); G06F 1/3293 (2013.01); G11C 5/14 (2013.01); H10B 10/00 (2023.02)] 17 Claims
OG exemplary drawing
 
1. A semiconductor integrated circuit comprising:
a first control part included in a first region in which a first operation speed is permitted;
a second control part included in a second region in which power supply is cut off in a power saving mode and in which operation at a speed higher than the first operation speed is required;
a memory having a specific function; and
a selection part selecting either a first path connecting the first control part and the memory or a second path connecting the second control part and the memory in response to a control signal.