US 12,243,581 B1
Output driver level-shifting latch circuit for dual-rail memory
Harold Pilo, Underhill, VT (US)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Feb. 16, 2023, as Appl. No. 18/110,789.
Int. Cl. G11C 11/4091 (2006.01); G11C 7/06 (2006.01); G11C 7/10 (2006.01); G11C 11/4094 (2006.01)
CPC G11C 11/4091 (2013.01) [G11C 7/065 (2013.01); G11C 7/1057 (2013.01); G11C 11/4094 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An output driver for a dual-rail memory comprising:
inversion circuitry configured to (i) receive voltage (VDDA) from a first power rail of the dual-rail memory, (ii) receive an output of a sense amplifier that senses a state of a bit cell of the dual-rail memory, and (iii) provide two outputs (QB, QT) having a voltage not greater than a voltage level of the first power rail; and
level-shifting circuitry configured to (i) receive the two outputs (QB, QT) of the inversion circuitry (ii) receive voltage (VDDP) from a second power rail of the dual-rail memory and (iii) drive an output (Q) based on the two outputs (QB, QT) of the inversion circuitry, the output (Q) having a voltage not greater than a voltage level of the second power rail, which is less than the voltage level of the first power rail.