US 12,243,578 B2
Read clock start and stop for synchronous memories
Aaron John Nygren, Boise, ID (US); Karthik Gopalakrishnan, Cupertino, CA (US); and Tsun Ho Liu, Boston, MA (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Dec. 20, 2023, as Appl. No. 18/390,431.
Application 18/390,431 is a continuation of application No. 17/850,658, filed on Jun. 27, 2022, granted, now 11,854,602.
Claims priority of provisional application 63/287,151, filed on Dec. 8, 2021.
Prior Publication US 2024/0119993 A1, Apr. 11, 2024
Int. Cl. G06F 12/00 (2006.01); G06F 1/08 (2006.01); G06F 1/10 (2006.01); G06F 3/06 (2006.01); G11C 11/4076 (2006.01); G06F 1/3234 (2019.01); G06F 1/3237 (2019.01); G06F 13/00 (2006.01)
CPC G11C 11/4076 (2013.01) [G06F 1/08 (2013.01); G06F 1/10 (2013.01); G06F 3/0604 (2013.01); G06F 3/0659 (2013.01); G06F 3/0671 (2013.01); G06F 1/3237 (2013.01); G06F 1/3275 (2013.01); G06F 12/00 (2013.01); G06F 13/00 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory controller, comprising:
a command queue including a plurality of entries for holding incoming memory access commands;
an arbiter for selecting commands from the command queue for dispatch to a memory; and
a read clock control circuit adapted to monitor read commands selected for dispatch to the memory and command the memory to change a state of a read clock from a first state in which the read clock provides a free-running clock signal that toggles continuously, to a second state in which the read clock provides a strobe signal that is active only in response to the memory receiving a read command.