US 12,243,576 B2
Memory calibration system and method
Jing Wang, Austin, TX (US); Kedarnath Balakrishnan, Bangalore (IN); Kevin M. Brandl, Austin, TX (US); and James R. Magro, Austin, TX (US)
Assigned to ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on May 17, 2023, as Appl. No. 18/198,709.
Application 18/198,709 is a continuation of application No. 16/938,855, filed on Jul. 24, 2020, granted, now 11,664,062.
Prior Publication US 2023/0368832 A1, Nov. 16, 2023
Int. Cl. G06F 9/24 (2006.01); G06F 1/3203 (2019.01); G06F 9/4401 (2018.01); G11C 11/406 (2006.01)
CPC G11C 11/40611 (2013.01) [G06F 1/3203 (2013.01); G06F 9/442 (2013.01); G11C 11/40615 (2013.01); G06F 9/4401 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for performing periodic calibrations of a data source impedance group associated with at least one dynamic random-access memory (DRAM), the method comprising:
signaling the at least one DRAM to perform periodic calibrations, wherein the signaling of the periodic calibrations cause a delay configured to allow a portion of the at least one DRAM to drain;
signaling the at least one DRAM to exit a power down state;
pre-charging addresses of the at least one DRAM associated with the data source impedance group; and
sending at least one periodic calibration command to the at least one DRAM, wherein the calibration causes the at least one DRAM to produce a tuning value accounting for voltage and temperature variations.