US 12,243,575 B2
Memory system having combined high density, low bandwidth and low density, high bandwidth memories
Sukalpa Biswas, Fremont, CA (US); and Farid Nemati, Redwood City, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Nov. 21, 2023, as Appl. No. 18/515,649.
Application 16/734,595 is a division of application No. 16/098,916, granted, now 10,573,368, issued on Feb. 25, 2020, previously published as PCT/US2017/020976, filed on Mar. 6, 2017.
Application 18/515,649 is a continuation of application No. 17/895,433, filed on Aug. 25, 2022, granted, now 11,830,534.
Application 17/895,433 is a continuation of application No. 17/140,753, filed on Jan. 4, 2021, granted, now 11,468,935, issued on Oct. 11, 2022.
Application 17/140,753 is a continuation of application No. 16/734,595, filed on Jan. 6, 2020, granted, now 10,916,290, issued on Feb. 9, 2021.
Claims priority of provisional application 62/355,012, filed on Jun. 27, 2016.
Prior Publication US 2024/0161804 A1, May 16, 2024
Int. Cl. G11C 11/402 (2006.01); G11C 5/02 (2006.01); G11C 5/04 (2006.01); G11C 5/06 (2006.01); G11C 7/02 (2006.01); G11C 11/406 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2023.01); H01L 25/10 (2006.01); H01L 27/02 (2006.01)
CPC G11C 11/4023 (2013.01) [G11C 5/025 (2013.01); G11C 5/04 (2013.01); G11C 5/06 (2013.01); G11C 5/063 (2013.01); G11C 7/02 (2013.01); G11C 11/40607 (2013.01); H01L 24/00 (2013.01); H01L 25/0652 (2013.01); H01L 25/105 (2013.01); H01L 25/0657 (2013.01); H01L 27/0203 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16225 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06541 (2013.01); H01L 2924/15311 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
at least one first integrated circuit including a first type of dynamic random access memory (DRAM);
at least one second integrated circuit including a second type of DRAM, wherein a second memory array in the second type of DRAM is less dense than a first memory array in the first type of DRAM and one or more accesses to the second memory array in the second type of DRAM are lower in energy consumption than accesses to the first memory array in the first type of DRAM, and wherein the first memory array comprises a first number of banks and the second memory array comprises a second number of banks, wherein the first number is less than the second number; and
a third integrated circuit including a memory controller configured to control access to a memory including the first type of DRAM and the second type of DRAM.