US 12,243,573 B2
Semiconductor devices including ferroelectric memory and methods of forming the same
Chenchen Wang, Hsinchu (TW); Sai-Hooi Yeong, Zhubei (TW); Chi On Chui, Hsinchu (TW); and Yu-Ming Lin, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jun. 29, 2023, as Appl. No. 18/343,972.
Application 17/814,755 is a division of application No. 17/099,094, filed on Nov. 16, 2020, granted, now 11,501,812, issued on Nov. 15, 2022.
Application 18/343,972 is a continuation of application No. 17/814,755, filed on Jul. 25, 2022, granted, now 11,727,976.
Claims priority of provisional application 63/059,214, filed on Jul. 31, 2020.
Prior Publication US 2023/0368830 A1, Nov. 16, 2023
Int. Cl. H01L 29/78 (2006.01); G11C 11/22 (2006.01); H01L 29/51 (2006.01)
CPC G11C 11/221 (2013.01) [H01L 29/516 (2013.01); H01L 29/78391 (2014.09)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a gate stack over a semiconductor substrate;
gate spacers along sidewalls of the gate stack;
a capacitor over the gate stack, the capacitor comprising:
a first electrode adjacent the gate spacers and over a top surface of the gate stack, wherein an inner sidewall of the first electrode tapers as the first electrode extends towards the semiconductor substrate;
a first ferroelectric layer over the first electrode, wherein the first ferroelectric layer extends over an uppermost surface of the first electrode in a cross-sectional view; and
a second electrode over the first ferroelectric layer.