US 12,243,557 B1
Write signal interference cancellation across data/servo clock boundary
Supaket Katchmart, San Jose, CA (US); and Mats Oberg, San Jose, CA (US)
Assigned to Marvell Asia Pte Ltd, Singapore (SG)
Filed by Marvell Asia Pte Ltd, Singapore (SG)
Filed on Mar. 20, 2024, as Appl. No. 18/610,540.
Application 18/610,540 is a continuation of application No. 18/344,472, filed on Jun. 29, 2023, granted, now 11,967,341.
Claims priority of provisional application 63/392,185, filed on Jul. 26, 2022.
This patent is subject to a terminal disclaimer.
Int. Cl. G11B 5/09 (2006.01); G11B 5/012 (2006.01); G11B 20/10 (2006.01)
CPC G11B 20/10009 (2013.01) [G11B 5/012 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A method for cancelling, from read signals in a read channel while a write channel is active, interference caused by write signals in the write channel, the method comprising:
generating a predicted channel response signal from the write signals in a write clock domain;
converting the generated predicted channel response signal using a write clock in the write clock domain having a rate corresponding to a read clock in a read clock domain;
transferring the converted predicted channel response signal from the write clock domain to the read clock domain and aligning phase of the transferred converted predicted channel response signal with phase of the read clock in the read clock domain;
synchronizing the phase-aligned transferred converted predicted channel response signal with the read signals; and
subtracting the synchronized phase-aligned transferred converted predicted channel response signal from the read signals.