US 12,243,499 B2
Gate driving circuit and display device
Youngjun Choi, Incheon (KR); and Sojung Lee, Gyeonggi-do (KR)
Assigned to LG DISPLAY CO., LTD., Seoul (KR)
Filed by LG DISPLAY CO., LTD., Seoul (KR)
Filed on Nov. 1, 2023, as Appl. No. 18/386,179.
Claims priority of application No. 10-2022-0176508 (KR), filed on Dec. 16, 2022.
Prior Publication US 2024/0203375 A1, Jun. 20, 2024
Int. Cl. G09G 3/36 (2006.01); G09G 3/32 (2016.01); G09G 3/3266 (2016.01)
CPC G09G 3/3677 (2013.01) [G09G 3/32 (2013.01); G09G 3/3266 (2013.01); G09G 2300/0426 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0291 (2013.01); G09G 2320/0295 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A gate driving circuit, comprising:
a plurality of stage circuits configured to output a plurality of scan signals, an nth stage circuit among the plurality of stage circuits including:
a scan output buffer circuit configured to receive a scan clock signal from a scan clock node, receive a low-potential voltage from a low-potential voltage node, and output a scan signal including a first signal section having a turn-off level voltage and a second signal section having a turn-on level voltage according to voltages of a Q node and a Qb node;
a control circuit including a plurality of transistors to control the voltages of the Q node and the Qb node to control an operation of the scan output buffer circuit, the plurality of transistors including a first Q node discharge transistor turned on or off by the voltage of the Qb node to control connection between the Q node and the low-potential voltage node; and
a body bias circuit configured to supply a body bias voltage to a body of the first Q node discharge transistor.