| CPC G09G 3/3266 (2013.01) | 25 Claims |
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1. A display panel comprising:
a base layer including a display region and a non-display region disposed adjacent to the display region;
a plurality of insulation layers disposed on the non-display region;
a pixel circuit disposed on the display region;
a light emitting element disposed on the display region and electrically connected to the pixel circuit;
a shielding electrode disposed on the non-display region; and
a scan driving circuit disposed on the non-display region, the scan driving circuit including a first transistor configured to output a scan signal of a first logic level during a turn-on period of the first transistor,
wherein the first transistor includes:
a first semiconductor pattern layer including:
a first input region,
a first output region, and
a first channel region disposed between the first input region and the first output region, the first channel region overlapping the shielding electrode;
a first gate electrode disposed on the first semiconductor pattern layer and overlapping each of the first channel region and the shielding electrode;
a second semiconductor pattern layer disposed on the first gate electrode, the second semiconductor pattern layer including:
a second input region electrically connected to the first input region through a first contact hole,
a second output region electrically connected to the first output region through a second contact hole, and
a second channel region disposed between the second input region and the second output region and overlapping the first channel region; and
a second gate electrode disposed on the second semiconductor pattern layer, overlapping the second channel region, and electrically connected to the first gate electrode, and
wherein, in a view perpendicular to an upper surface of the base layer, the shielding electrode is disposed between and spaced apart from each of the first contact hole and the second contact hole.
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