| CPC G09G 3/325 (2013.01) [G09G 3/3291 (2013.01); G09G 2230/00 (2013.01); G09G 2300/0852 (2013.01); G09G 2310/0251 (2013.01); G09G 2320/0233 (2013.01); G09G 2320/0257 (2013.01); G09G 2320/045 (2013.01); H10K 59/1213 (2023.02); H10K 59/1216 (2023.02); H10K 59/131 (2023.02)] | 21 Claims |
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1. An organic light emitting display apparatus, comprising:
a display panel including a plurality of pixels, at least one of the plurality of pixels including an organic light emitting diode and a pixel circuit,
wherein the pixel circuit includes a driving transistor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first capacitor, a second capacitor, a first node which is a gate electrode of the driving transistor, a second node which is a source electrode of the driving transistor, a third node which is a drain electrode of the driving transistor, and a fourth node which is an anode electrode of the organic light emitting diode,
wherein:
the first transistor is configured to supply a reference voltage to the first node in accordance with a first scan signal,
the second transistor is configured to control an electrical connection between the first node and a data line in accordance with a second scan signal,
the third transistor is configured to control an electrical connection between the second node and a high potential voltage line in accordance with a first emission signal,
the fourth transistor is configured to control an electrical connection between the third node and the fourth node in accordance with a second emission signal,
the fifth transistor is configured to supply a first bias voltage to the fourth node in accordance with a third scan signal,
the first capacitor is disposed between the first node and the second node, and
the second capacitor is disposed between the high potential voltage line and the second node,
wherein one frame is divided into a refresh period in which a data voltage is written and a hold period in which the data voltage written in the refresh period is held, the refresh period including a first driving period to a fourth driving period, and
during the first driving period, the first transistor is on while the third transistor is on responsive to a gate electrode of the first transistor receiving the first scan signal at an on-level and a gate electrode of the third transistor receiving the first emission signal at the on-level, and the second transistor, the fourth transistor, and the fifth transistor are all turned off responsive to a gate electrode of the second transistor receiving the second scan signal at an off-level, a gate electrode of the fourth transistor receiving the second emission signal at the off-level, and a gate electrode of the fifth transistor receiving the third scan signal at the off-level.
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