US 12,243,482 B2
Display device and display correction system
Shunpei Yamazaki, Setagaya (JP); Hajime Kimura, Atsugi (JP); and Tatsuya Onuki, Atsugi (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Appl. No. 18/036,221
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
PCT Filed Nov. 24, 2021, PCT No. PCT/IB2021/060902
§ 371(c)(1), (2) Date May 10, 2023,
PCT Pub. No. WO2022/118141, PCT Pub. Date Jun. 9, 2022.
Claims priority of application No. 2020-202340 (JP), filed on Dec. 6, 2020; application No. 2020-205895 (JP), filed on Dec. 11, 2020; and application No. 2021-028883 (JP), filed on Feb. 25, 2021.
Prior Publication US 2023/0410738 A1, Dec. 21, 2023
Int. Cl. G09G 3/3233 (2016.01)
CPC G09G 3/3233 (2013.01) [G09G 2300/0814 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0626 (2013.01); G09G 2330/021 (2013.01); G09G 2330/10 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A display device comprising:
a pixel circuit; a driver circuit; and a functional circuit,
wherein the driver circuit is configured to output a signal for performing display in the pixel circuit,
wherein the functional circuit comprises a CPU comprising a CPU core comprising a flip-flop electrically connected to a backup circuit,
the display device further comprising:
a first transistor and a second transistor;
an insulator over the first transistor and the second transistor; and
a third transistor and a fourth transistor over the insulator,
wherein the driver circuit comprises the first transistor,
wherein the flip-flop comprises the second transistor,
wherein the pixel circuit comprises the third transistor, and
wherein the backup circuit comprises the fourth transistor.