| CPC G09G 3/3233 (2013.01) [G09G 3/3266 (2013.01); G09G 3/3283 (2013.01); G09G 2310/08 (2013.01); G09G 2320/043 (2013.01); G09G 2320/0686 (2013.01); G09G 2330/021 (2013.01)] | 19 Claims |
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1. A display device comprising:
a display panel comprising a plurality of pixels respectively connected to corresponding data lines of a plurality of data lines and respectively connected to corresponding scan lines of a plurality of scan lines;
a data driving circuit which drives the plurality of data lines;
a scan driving circuit which drives the plurality of scan lines in response to clock signals; and
a driving controller which:
divides the display panel into a first display area and a second display area;
controls the data driving circuit and the scan driving circuit so that the first display area is driven at a first driving frequency, and the second display area is driven at a second driving frequency lower than the first driving frequency during a multifrequency mode; and
divides the second display area into a plurality of blocks and drives a block of the plurality of blocks every frame during the multi-frequency mode,
wherein the driving controller controls, in a normal mode, the data driving circuit and the scan driving circuit so that the first display area and the second display area are driven at a normal frequency,
the second driving frequency is lower than the normal frequency, and
the first driving frequency is higher than the normal frequency,
wherein the driving controller controls the data driving circuit and the scan driving circuit so that the first display area and a first block among the plurality of blocks of the second display area are sequentially driven during a first frame of the multi-frequency mode,
wherein the driving controller controls the data driving circuit and the scan driving circuit so that the first display area and a second block among the plurality of blocks of the second display area are sequentially driven during a second frame consecutive to the first frame of the multi-frequency mode,
wherein the second frame comprises a first period, a delay period consecutive to the first period and a second period consecutive to the delay period,
wherein the driving controller provides a first area image signal corresponding to the first display area to the data driving circuit during the first period,
wherein the driving controller provides a second block image signal corresponding to the second block to the data driving circuit during the second period,
a first clock signal among the clock signals has a first frequency during each of the first period and the second period, and
the first clock signal has a second frequency that is higher than the first frequency during the delay period.
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