US 12,243,460 B2
Display panel, integrated chip, and display apparatus
Yuheng Zhang, Wuhan (CN); and Jiemiao Pan, Wuhan (CN)
Assigned to Hubei Yangtze Industrial Innovation Center Of Advanced Display Co., Ltd., Wuhan (CN)
Filed by Hubei Yangtze Industrial Innovation Center Of Advanced Display Co., Ltd., Wuhan (CN)
Filed on Dec. 4, 2023, as Appl. No. 18/528,719.
Application 18/528,719 is a continuation of application No. 17/810,615, filed on Jul. 4, 2022, granted, now 11,875,717.
Claims priority of application No. 202111673899.X (CN), filed on Dec. 31, 2021.
Prior Publication US 2024/0105095 A1, Mar. 28, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G09G 3/20 (2006.01); G09G 3/3233 (2016.01)
CPC G09G 3/20 (2013.01) [G09G 3/3233 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/0237 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0233 (2013.01); G09G 2320/0626 (2013.01); G09G 2330/023 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A display panel, comprising:
a pixel circuit and a light emitting element;
wherein the pixel circuit comprises a drive module, and a bias adjustment module; wherein
the drive module comprises a drive transistor;
wherein the bias adjustment module is configured to provide a bias adjustment signal to a first pole of the drive transistor or a second pole of the drive transistor;
wherein:
data refresh frequencies of the display panel comprise a first data refresh frequency F1 and a second data refresh frequency F2, wherein F1>F2;
at the first data refresh frequency F1, the bias adjustment signal is Vf1, and at the second data refresh frequency F2, the bias adjustment signal is Vf2, wherein Vf1≠Vf2; and
an operation process of the pixel circuit comprises a data writing frame and a holding frame;
the bias adjustment signal is Vf11 in the data writing frame at the first data refresh frequency F1, and the bias adjustment signal is Vf12 in the data writing frame at the second data refresh frequency F2; the bias adjustment signal is Vf21 in the holding frame at the first data refresh frequency F1, and the bias adjustment signal is Vf22 in the holding frame at the second data refresh frequency F2; and |Vf11−Vf12|=|Vf21−Vf22|;
or, wherein:
data refresh frequencies of the display panel comprise a first data refresh frequency F1 and a second data refresh frequency F2, wherein F1>F2;
at the first data refresh frequency F1, the bias adjustment signal is Vf1, and at the second data refresh frequency F2, the bias adjustment signal is Vf2, wherein Vf1 #Vf2; and
an operation process of the pixel circuit comprises a data writing frame and a holding frame;
the bias adjustment signal is Vf11 in the data writing frame at the first data refresh frequency F1, and the bias adjustment signal is Vf12 in the data writing frame at the second data refresh frequency F2; the bias adjustment signal is Vf21 in the holding frame at the first data refresh frequency F1, and the bias adjustment signal is Vf22 in the holding frame at the second data refresh frequency F2; and |Vf11−Vf12|>| Vf21−Vf22|, or,
|Vf11−Vf12|<|Vf21−Vf22|;
or, wherein:
data refresh frequencies of the display panel comprise a first data refresh frequency F1 and a second data refresh frequency F2, wherein F1>F2; and
at the first data refresh frequency F1, a duration of a bias adjustment stage in one data refresh period is T1, and at the second data refresh frequency F2, a duration of a bias adjustment stage in one data refresh period is T2, wherein T1≠T2.